The high performance readout chain for the DSSC 1Megapixel detector, designed for high throughput during pulsed operation mode

• Verfasst von: Tangl, Manfred [VerfasserIn]
• Verfasst von: Soldat, Jan [VerfasserIn]
• Verfasst von: Kugel, Andreas [VerfasserIn]
• Verfasst von: Donato, Mattia [VerfasserIn]
• Verfasst von: Porro, Matteo [VerfasserIn]
• Verfasst von: Fischer, Peter [VerfasserIn]
• Titel: The high performance readout chain for the DSSC 1Megapixel detector, designed for high throughput during pulsed operation mode
• Verf.angabe: M. Kirchgessner, J. Soldat, A. Kugel, M. Donato, M. Porro, P. Fischer
• E-Jahr: 2015
• Jahr: 12 January 2015
• Fussnoten: Gesehen am 26.10.2017
• Titel Quelle: Enthalten in: Journal of Instrumentation
• Ort Quelle: London : Inst. of Physics, 2006
• Jahr Quelle: 2015
• Band/Heft Quelle: 10(2015), 1, Artikel-ID C01011, Seite ?
• ISSN Quelle: 1748-0221
• DOI: doi:10.1088/1748-0221/10/01/C01011
• Datenträger: Online-Ressource
• Sprache: eng
• K10plus-PPN: 1564812618

Abstract

The readout chain of the DSSC 1M pixel detector currently built at DESY, Hamburg for the European X-Ray Free Electron Laser is described. The system operates in pulsed operation mode comparable to the new ILC. Each 0.1 seconds 800 images of 1M pixels are produced and readout by the DSSC DAQ electronics. The total data production rate of the system is about 134 Gbit/s. In order to deal with the high data rates, latest technology components like the Xilinx Kintex 7 FPGA are used to implement fast DDR3-1600 image buffers, high speed serial FPGA to FPGA communication and 10 GB Ethernet links concentrated in one 40 Gbit/s QSFP+ transceiver.