| Online-Ressource |
Verfasst von: | Aamir, Syed Ahmed [VerfasserIn]  |
| Stradmann, Yannik [VerfasserIn]  |
| Müller, Paul [VerfasserIn]  |
| Pehle, Christian [VerfasserIn]  |
| Hartel, Andreas [VerfasserIn]  |
| Grübl, Andreas [VerfasserIn]  |
| Schemmel, Johannes [VerfasserIn]  |
| Meier, Karlheinz [VerfasserIn]  |
Titel: | An accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture |
Verf.angabe: | Syed Ahmed Aamir, student member, IEEE, Yannik Stradmann, Paul Müller, Christian Pehle, Andreas Hartel, Andreas Grübl, Johannes Schemmel, member, IEEE, and Karlheinz Meier, member, IEEE |
E-Jahr: | 2018 |
Jahr: | 27 June 2018 |
Umfang: | 14 S. |
Fussnoten: | Gesehen am 02.04.2019 |
Titel Quelle: | Enthalten in: Institute of Electrical and Electronics EngineersIEEE transactions on biomedical circuits and systems |
Ort Quelle: | New York, NY : IEEE, 2007 |
Jahr Quelle: | 2018 |
Band/Heft Quelle: | 65(2018), 12, Seite 4299-4312 |
ISSN Quelle: | 1940-9990 |
Abstract: | We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaled-down prototype high input count analog neural network with digital learning system chip. Designed as continuous-time circuits, the neurons are highly tunable and reconfigurable elements with accelerated dynamics. Each neuron integrates input current from a multitude of incoming synapses and evokes a digital spike event output. The circuit offers a wide tuning range for synaptic and membrane time constants, as well as for refractory periods to cover a number of computational models. We elucidate our design methodology, underlying circuit design, calibration, and measurement results from individual sub-circuits across multiple dies. The circuit dynamics matches with the behavior of the LIF mathematical model. We further demonstrate a winner-take-all network on the prototype chip as a typical element of cortical processing. |
DOI: | doi:10.1109/TCSI.2018.2840718 |
URL: | Bitte beachten Sie: Dies ist ein Bibliographieeintrag. Ein Volltextzugriff für Mitglieder der Universität besteht hier nur, falls für die entsprechende Zeitschrift/den entsprechenden Sammelband ein Abonnement besteht oder es sich um einen OpenAccess-Titel handelt.
Volltext: https://doi.org/10.1109/TCSI.2018.2840718 |
| DOI: https://doi.org/10.1109/TCSI.2018.2840718 |
Datenträger: | Online-Ressource |
Sprache: | eng |
Sach-SW: | 65nm CMOS |
| accelerated dynamics |
| accelerated LIF neuronal network array |
| Analog integrated circuits |
| analog network core |
| Biological system modeling |
| circuit design |
| circuit dynamics |
| CMOS integrated circuits |
| Computational modeling |
| Computer architecture |
| continuous-time circuits |
| cortical processing |
| design methodology |
| digital learning system chip |
| digital spike event output |
| high input count analog neural network |
| input current |
| integrated circuit design |
| Integrated circuit modeling |
| integrated circuit modelling |
| leaky integrate and fire |
| leaky integrate-and-fire neuron circuit design |
| LIF mathematical model |
| membrane time constants |
| mixed analogue-digital integrated circuits |
| mixed-signal neuromorphic architecture |
| multiple dies |
| neural chips |
| neural net architecture |
| neuromorphic |
| Neuromorphics |
| neuronal array |
| Neurons |
| opamp |
| OTA |
| prototype chip |
| prototype high input count analog neural network |
| refractory periods |
| second-generation BrainScaleS mixed-signal CMOS neuromorphic hardware |
| size 65 nm |
| spiking neuron |
| Synapses |
| tunable resistor |
| winner-take-all network |
K10plus-PPN: | 1662699956 |
Verknüpfungen: | → Zeitschrift |
¬An¬ accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture / Aamir, Syed Ahmed [VerfasserIn]; 27 June 2018 (Online-Ressource)